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quality is our message mt5f18467 -1- m-power 2a mp2aseries application note (ver.1.1) ver.1.1 2007.01.12
quality is our message mt5f18467 -2- contents 1. outline 2. features 3. line up 4. description of the multi-oscillated current resonant circuit 4 ? 1. basic circuit configuration and operation 5. description of m-power 2a 5 ? 1. block diagram 5 ? 2. external drawing 5 ? 3. descript ion of pin functions 5 ? 4. circuit block descriptions ? power supply control voltage ? q1 pulse width control circuit ? mosfet drive, dead time ? protection functions and latched shutdown 5 ? 5. internal structure 6. design advices 6 ? 1. setting resonant conditions 6 ? 2. startup circuit, v cc winding circuit and mainta ining a latched shutdown 6 ? 3. q2 gate pin 6 ? 4. vw pin 6 ? 5. con pin 6 ? 6. vref pin 6 ? 7. i s pin 6 ? 8. fb pin warning
quality is our message mt5f18467 -3- 1. outline in recent years switching power supplies have been required to be not only compact and light weight but also to hav e low power consum ption and a high power fa ctor. a current resonant converter is applied, because it is superior to other topology fr om the viewpoint of low noise and efficiency. however at li ght loads efficiency is lo w and several watts of lo ss occur even at no load. this means that a sub-power supply is required at standby time whic h adds to the size of the unit. fuji electric has utilized the advantages of the current reson ant converter and developed a new multi-oscillated current re sonant converter with contro llability that allows ea sy power supply design (control method : combine pwm contro l and self-oscillated control). the m-power2a series of special power devi ces have been developed for the converter. these multiple-chip power devices incorporate two-mosfet and a special control ic in one package. when the m-power2a is used with the multi-oscillated current resonant converter, energy is conserved at standby mode withou t a sub-power supply. also when the m-power2a is combined with a pfc circuit, a switching power supply for high power factors can easily be designed . 2 features 2-1 high efficiency, low noise ? two-mosfet (q1, q2) so ft switching operation ? low-noise secondary-side diode (no surge voltage at reverse recovery) ? multi-oscillation means limited increase in frequency for light loads (frequency increase of 20% of rated load for rate d 10% load) and limited reactive power of transformer magnetizing current. 2-2 fail-safe design: it is easy to co nstruct a fail-safe power supply system. ? protection functions with latch shutdown: ov er current (oc), over voltage (ov), and over heating (oh). 3. lineup v ds r ds (on) v ds r ds (on) v cc (on) tj(oh) mp2a5038 500v 0.38 ? 500v 0.38 ? mp2a5050 500v 0.5 ? 500v 0.5 ? MP2A5060 500v 0.6 ? 500v 0.6 ? mp2a5077 500v 0.77 ? 500v 0.77 ? mp2a2013 250v 0.125 ? 250v 0.125 ? type name 16.5v 125 150 mos-fet (q1) mos-fet (q2) control ic
quality is our message mt5f18467 -4- 4. description of the multi-oscillated current resonant circuit 4-1 description of basic circui t configuration and operation 1) basic circuit configuration figure 1 shows the basic configurat ion of a multi-oscillated current resonant circuit that uses the m-power2a. with this method current resona nce is performed using the series resonant circuit of a leakage inductance of the transformer and capacitor cr. the q1 mosfet performs pwm oscillation driven by the control ic and t he q2 mosfet performs self-oscillation driven by the drive winding of the transformer tr. control ic m-power 2a q1 q2 vq1 vq2 iq2 iq1 vg2 vg1 id2 vo ed pwm control self-oscilation r1 r2 p3 vp1 id1 d1 d2 c r p1 p2 s1 s2 t r output voltage regulator circuit rectifier circuit or pfc vp3 fig.1 basic circuit configuration
quality is our message mt5f18467 -5- 2) operation this section describes the op eration of the multi-oscillat ed current resonant circuit. figure 2 shows the timi ng chart and figure 3 sh ows the current path dur ing periods i to vi. state i vq1 vq2 vq1,vq2 0 iq2 iq1 iq1,iq2 0 vp1 vp1 vp3 0 id1 id2 id1,id2 0 vp2 vg2 0 dead time for prevention of arm short td vg1 0 0 voltage reference reference signal value voltage reference reference signal value vgs(th) vp2 vg2 vp3 fig.2 timing diagram
quality is our message mt5f18467 -6- figure 3 shows the current path during periods i to vi. in figures 3.1 to 3.6, capacito rs cq1 and cq2 show the output ca pacity of q1 and q2, diodes dq1 and dq2 indicate the q1 and q2 body diodes, lm indicates the t1 exciting inductance, and ri indicates the load. li indicates the inductance fo r the resonant current sent to the secondary side load and is included in the figure 3 circuit drawings to assist the description of the operation in this section. ntlp:callouts fig. 3.1 current path for period i fig. 3.2 current path for period ii fig. 3.3 current path for period iii fig. 3.4 current path for period iv fig. 3.5 current path for period v fig. 3.6 current path for period v fig. 3 current paths for periods i to vi ll fig.3.1 current path at state i ed d1 d2 q2 q1 cr ll t1 co cq2 cq1 dq2 dq1 rl fig.3.5 current path at state v fig.3.2 current path at state ii ed ed d1 d2 q2 q1 cr ll t1 co cq2 cq1 dq2 dp1 rl q2 q1 cr ll t1 cq2 cq1 dq2 dq1 l m l m l m fig.3.4 current path at state iv ed q2 q1 cr ll t1 cq2 cq1 dq2 dq1 d1 d2 co rl l m d1 d2 co rl cr fig.3.1 current path at state vi fig.3.3 current path at state iii ed ed d1 d2 d1 d2 q2 q1 t1 co cq2 cq1 dq2 dq1 rl q2 q1 cr ll t1 co cq2 cq1 dq2 dq1 rl l m l m fig. 3 current path during period i to vi
quality is our message mt5f18467 -7- period i (fig. 3.1) q1 is on, q2 is off, and th e current flows through the circ uit shown in solid lines in the diagram. if the currents that flows to cr, ll, and lm are indicated as i c , i li , and i lm , equation (1) is true. i cr = i li + i lm ??.. (1) equation (2) is true based on the product of ampere turns (at). n p1 i l1 = n s1 i d1 ?. (2) np1: number of p1 windings; ns1: number of s1 windings; i d1 : d1 current power continues to be su pplied to the load and accu mulates at ll and lm. period ii (fig. 3.2) when q1 turns off, cq1 is charged using the en ergy accumulated at ll and lm and cq2 is discharged. equations (1 ) and (2) above and equations (3 ) and (4), below, are true during this period. i cr = i cq1 + i cq2 ?.. (3) i cq1 = i cq2 ?.. (4) i cq1 : cq1 current; i cq2 : cq2 current the rate of the q1 voltage increase is rest rained therefore, by th e charging speed of cq1 and the rate of the q2 voltage decrease is restrained by t he discharging speed of cq2. period iii (fig. 3.3) dq2 conducts current when th e cq1 voltage reaches the dc bus voltage ed and cq2 reaches zero voltage, and the current flows through the path indicate d in the figure 3.3. therefore the q2 voltage is clamped by ed. during this period, equations (1) and (2) above and equat ion (5), below, are true. i cr = i dq2 ?.. (5) i dq2 : dq2 current when current is flowing to dq2, zero volta ge switching (zvs) operat ion is achieved by providing current to q2. period iv (fig. 3.4) the transformer primary-side current is in verted and the current flows through the path indicated in figure 3.4. eq uations (1) and (2) hold even during this period. also, energy is accumulated at ll and lm.
quality is our message mt5f18467 -8- period v (fig. 3.5) q2 turns off, cq1 is discharg ed, and cq2 is charged by t he energy accumulated at ll and lm. equations (1), (2), (3), and (4) are tr ue during this period. t herefore, the rate of voltage decrease for q1 is re strained by the discharging sp eed of cq1 and the rate of voltage increase for q2 is restrai ned by the charging speed of cq2. period vi (fig. 3.6) dq1 conducts current when cq1 reaches zero voltage and cq2 voltage reaches ed. therefore, q1 voltage is clamped by ed. during this pe riod, equations (1), (2), and (6), below, are true. i cr = i dq1 ?.. (6) i dq1 : dq1 current when current is flowing to dq1, zero voltag e switching (zvs) oper ation is achieved by turning on q1. in other words, i lm current circulates around the prim ary side and the secondary side load is supplied at the secondary c onversion value of the i li current.
quality is our message mt5f18467 -9- 5. description of m-power2a 5 - 1. block diagram figure 4 shows the block diagram of the m-power2a. p gnd s1 vref vw con fb d1 s2 d2 g2 14 23 20 vcc 11 15 13 22 d2 s1 doc rout vz uvl o bandga p ref enb vref vr2 5 (5.0v) (2.5v) vcc rch k vcc(on) vccl(off) 7.5 v vw h vw l vcc one tim e latch vw cp dela y lv(5v) controlled bloc k vr25 vref enb ifb pwm oc vre f( on) vre f( off) 4 v ion(dis) ion(chg) r s rs-ff q qb ion(plu) o h tjoh doh v r r sb rs-ff q qb st ar t b dela y r sb rs-ff q qb enb r s rs-ff q qb frb dela y enb rest art ovcp vc ch( off) enb vr25 do v do v 100us hold & 36ms ec time r 270us time r rfb d r d-ff q h qb cb 10 12 7 s gnd is 18 19 d1 s2 5 4 8 fig. 4 m-power 2a block diagram
quality is our message mt5f18467 -10- 5-2. external drawing figure 5 shows an external drawing of the m-power2a. units: mm fig. 5 external drawings: f219 forming
quality is our message mt5f18467 -11- 5-3. description of pin functions table 1 pin functions note: * pins 3, 17, and 21 are cut. * pins 1, 2, 6, a nd 16 have no pin frames. * pin 9 is disconnected. this pin is connected to the q1 gate but neve r connect it for wavefo rm observation or any other purpose. connection of the pin 9 could lead to major pr oblems and could destroy the m-power2a. termainal symbol function 4, 5 s1 mosfet (q1) source 7s-gnd signal-ground (v ref , fb, con, vw) 8p-gnd power-ground (v cc , is) 10 v cc power supply 11 v ref reference voltage output 12 is over current detection 13 fb feedback signal input for constant voltage control 14 con reference oscillation of q1 on-time 15 vw q1 turn on and off timing detection 18, 19 d1, s2 q1 drain and q2 source 20 g2 q2 gate 22, 23 d2 q2 drain
quality is our message mt5f18467 -12- 5-4. circuit block descriptions (1) power supply control voltage 1) v cc (on) or less to ensure that the ic is in a completely operable status befor e the internal ic outputs are enabled, two low-voltage lockout comparators, uvlo and rchk, are built in to moni tor the power supply voltage v cc and the reference voltage vref levels. 2) vcc (on) : operation startup voltage and startup current the uvlo on threshold v cc(on) ranges between 15. 5 and 17.5v. the switching operation starts when vcc reaches v cc(on) . the current (icc) flowing to the ic just prior to the start of ic operation is exceptiona lly small. refer to the vcc-icc current diagram in the delivery specifications for details. 3) v ccl(off) : operation stop (insufficient) voltage the uvlo off threshold v ccl(off) ranges between 8.0 and 10.0v. this is the value of v cc at which the swit ching operation is stopped when v cc decreased from its value during operating status. 4) v cc h= v cc (on) v cc l(off) : hysteresis width the threshold voltage to turn the uvlo on and off has hyst eresis. the hysteresis width is 7.5v (typical). 5) v cch(off) : over voltage threshold voltage v cch(off) is the over voltage (ov) comparator threshol d voltage and it is the value of v cc at which a latched shut down occurs when v cc increases above this v cch(off) value. 6) v cc(la) : latch-stop cancellation voltage v cc(la) is the value of v cc at which the latc h is released when v cc decreases after a latched shutdown has occurred for an ov er voltage or over current. 7) zener diode a zener diode with a withstan d voltage of approximately 30v is built-in between v cc (pin 10) and s gnd (pin 7) to protect the ic. 8) recommended operating range the recommended v cc range for normal operation is 19.0 to 20.0v item 28.0[v] vcch(off) 24.0[v] normal 24.0[v] operation ( caution : 9.9 [v] vccl ( off ) 7.9 [v] 4.1[v] vcc(la) 0.9[v] vcc voltage fig. 6 control voltage and operating switching points
quality is our message mt5f18467 -13- 9) current consumption the current consumption de pends on the model, v cc (pin 10) voltage, operating frequency, and operating status (normal op eration or latched oper ation). refer to th e vcc-icc and fc-icc diagrams in the delivery specificat ions for your model for details. 2 q1 pulse width control circuit figure 7 shows a schematic block diagram of th e q1 drive circuit and figure 8 shows the q1 pulse width controlled timing chart. polarity discrimination circuit q1 q2 vp1 vq1 vq2 iq2 iq1 vg2 vg1 id1 id2 vo ed r1 r2 d1 d2 c r p1 p2 p3 s1 s2 t r pc1 output voltage regulator circuit vp3 m-power 2a vwh vwl vw cp r s rs-ff q q1 gate restart delay-1 15 vw ifb rfb pwm cp 4v ion(chg) ion(plu) vr ion(dis) 13 14 con fb pc1 7 vcc fig. 7 q1 drive circuit block
quality is our message mt5f18467 -14- the q1 pulse width control circuit holds steady the output voltage. t he input signals for this circuit are the output signal vw from the winding voltage polarity discrimination circuit and the voltage reference value v fb which holds the outp ut voltage steady. in the circuit shown in figure 7 the auxiliary winding volta ge for control power supply (v cc ) is negative and the vw voltage reache s zero level while q2 is on. when q2 turns off, the auxiliary winding voltage becomes positive and vw exceeds the th reshold value vwh. t he q1 on time is determined by this timing. in additi on a capacitor time setting is nee ded in the vw circuit so that the gate signal is out put after q1 voltage reaches zero. the voltage reference v fb is generated by the output volt age adjustment circuit generating a signal for deviation from the se t output voltage value, isolating the deviation signal using photo vfb, vc on a t s tartup a t normal operation gate puls e res et at vw < vwl gate puls e res et at vfb < vc on the tim ing for s etting the gate pulse is vwh > vw(th ). v w vg1 vp1 vg2 vq2 , iq2 vq1 , iq1 vgs(th ) vq2 iq2 vq1 iq1 vcon reference signal vfb reference signal vwh ,vwl vo set voltage fig. 8 q1 pulse width control timing chart
quality is our message mt5f18467 -15- isolator pc1 and converting it to the collector voltage value for the transistor on th e light-receiving side. during normal operat ion, the size of th e reference signal v con value, which increases in proportion from the time when the voltage reference value v fb and the auxiliar y winding voltage turn positive, is compared usin g the comparator pwmcp. the rs flip-flop ft1 is set and q1 turns off when the referenc e signal value exceeds the voltage reference value. when q1 turns off, the q2 gate vo ltage vg2 goes from negative to positive and q2 turns on when vg2 exceeds the q2 gate threshold value vgs(th). the reference signal v con will return to the default setting after q1 has turn ed off and when it drops below vwl. at startup, the tran sformer winding voltage vp1 (r efer to fig. 1) may sw itch from positive to negative before the reference signal exceeds the voltage reference value after q1 has turned on. to prevent arm short circuits in such circumstances, the m-power 2a has a function to force q1 off when vw has dropped below the threshol d value voltage vwl, before the transformer winding voltage vp1 switches from positive to negative. (3) mosfet drive, dead time the q1 in the mosfet is driven directly by th e control ic. the circui t in the output section from the control ic consists of a cmos push-pull ci rcuit and the mosfet gates provide a full swing to the vcc voltage. the wire inductance between the mo sfet and the control ic is extremely small, eliminating ma lfunction. there is a dead time between when the vw voltage signal exceeds vwh to when q1 turns on to pr event arm short circuits when q1 turns on. for safety the output stage from the c ontrol ic has a built -in resistor of 10k ? between g and s enabling the q1 drain voltage to be applied even when there is no v cc . for example, during the latch protection operation, there is no chance of destruction even if the ac input remains supplied. (4) protection functions and latched shutdown ? over current protection the following form of over curre nt protection is built in to protect the m-power2a and power supply even if there is a problem with the load. over current (oc) protection and pu lse-by-pulse oper ation voltage: v oc a latched shutdown operation is also provided for over current and short circuit current to ensure stopping for any problems . when stopped, the co ntrol ic drive output maintains a sinking status. a 36ms dead timer is prov ided for an over current latched shutdown. this is to prevent protection from operating for over current such as the charge current for an electrolytic capacitor on the load side when starting. ? over voltage protection a latched shutdown is impl emented if the m-power2a v cc pin voltage exce eds the operation stop over voltage v cch(off) . ? over heating protection over heating protection (t joh ) is built into the control ic. if the temperature of the control ic
quality is our message mt5f18467 -16- increases to the over heating protection (t joh ) operating point due to a problem in the load or other cause, a latched shutdown (36m s timer latch) is implemented. the latched shutdown is released by reducing the power supply voltage v cc to the latch release voltage v cc(la) or less. the following table lists the spec ifications of the latched shutdo wn implemented as a protection function. 5-5. internal structure as shown in figure 9, q1 q2 and the control ic are die-bond ed in three frames and are connected between the frames using aluminum wire. in other words a discret e device structure is used without a ceramic board such as the ones used in hybrid ic structures or other wiring boards. there are thus fewer structural parts assembly processing is faster and a si mple highly reliable structure is achieved. the m-power2a uses full-molded structures without any poles on the rear side. the structure also provides adequate insulation between q1, q2, and the control ic. q1 q2 ic fig.9 internal structure no. protection function latched shutdown specifications 1 over current protection(oc) when an over current is detected on vcc for 36ms or longer a latched shutdown is implemented(timer latch). 2 over voltage protection(ov) a latched shutdown is implemented when v cch (off) is detected once. 3 over heat protection(oh) when a temperature higher than tjoh is detected for 36ms or longer a latched shutdown is implemented(timer latch).
quality is our message mt5f18467 -17- 6 design advices 6-1 setting resonant conditions: figure 10 shows the transfor mer configuration. (1) maximum power po(max) : calculating po(max) pcr(max): the maximum power supplied fr om the resonant capacitor cr. the following equation can be used to calculate pcr(max) assuming that the re sonant capacit or's voltage amplitude equals t he dc bus voltage (e d) when the power supplied from the resonant capacitor is at its maximum value. fr ed cr = ) cr ( p 2 (6-1) fr: resonant frequency calculate the resonant freque ncy (fr) with the following equation. ls cr 2 1 = fr (6-2) ls: inductance in primary with one of the secon dary windings (either s1 or s2) short-circuited. the power supplied from the reso nant capacitor is t he component of the po wer supplied in the secondary and the transf ormer's magnetizing energy (reactive power.) magnetizing energy: plm(max) calculate the transformer's peak magnetizing current (ilmp) with the following equation. fr ? lm ? 4 vo ? n = fr ? 2 1 lm vo ? n 2 1 = ilmp equation 6-3 yields the maximu m magnetizing energy plm(max). in this equation lo is the primary winding inductance when secondary windings are open vo is the output voltage and n is the turn ratio (np1/np2.) () fr ? lo 16 vo ? n = fr ) ilmp ( lo = (max) plm 2 2 (6-3) maximum power supplied to secondary: po(max) the results from equations 6- 1 and 6-3 can be used to find po(max) using equation 6-4. () fr ? lo 16 vo ? n fr ? ed ? cr = (max) plm (max) pcr = (max) po 2 2 (6-4) (2) method for setting t he resonant conditions maximum power po(max) : setting po(max) when actually design ing the system the effect of the conversion efficiency ( ) on the power supply maximum load (pload(max )) must be taken into account when calculati ng the maximum power (po(max).) d1 d2 cr s1 s2 t r p1 fig. 10 transformer configuration
quality is our message mt5f18467 -18- (max) pload = (max) po (6 \ 5) the conversion efficiency ( ) is about 0.9. setting lo : the inductance lo when tran sformer's secondary windings are open. in order for q1 and q2 to provide zero volta ge switching the transfor mer's magnetizing energy must be greater than the energy involved in char ging/discharging the output capacitance of q1 and q2. consequently the inductance when t he transformer's secondary is open (lo) is set between 1.0 and 2.0mh. setting fr : the resonant frequency: fr and minimum switching frequency :fs(min). since the secondary diodes (ds1 and ds2) have current flowing continuously (without pause), design the resonant frequency (f r) so that the minimum switchin g frequency (fs(min)) is about 10% higher than the resonant frequency (fr). we recommend de signing the res onant frequency at about 70khz to 80khz. dc bus voltage : ed when setting the maximum power use the minimum value for the dc bus voltage (ed(min).) setting the resonant capacitance (cr) and inductance when the tran sformer's secondary winding is shorted (ls.) enter the values set in steps 1 through 4 (po(ma x), lo, fr, n, vo, and ed(min)) into equation 6-4 to calculate cr. next, enter cr into equation 6-2 to calculate ls. setting example setting conditions: with pload(max) = 80w, vo = 15v, ed(min) = 400v, lo = 2mh, fr = 80khz, and n = 80/6 = 13.33 (np = 80 turns, ns1 = ns2 = 6 turn s), po can be calculated as follows: po = 80 0.9 = 88.89w the resonant capacitance (cr) can be calculated fr om equation 6-4: () ( ) 3 2 3 3 2 2 2 10 80 400 10 80 10 2 16 15 33 . 13 89 . 88 (min) 16 (max) + = + = fr ed fr lo vo n po cr = 7.3n ls can be calculated from equation 6-2: () () h fr cr ls 542 2 10 80 10 3 . 7 1 2 1 3 9 2 = = =
quality is our message mt5f18467 -19- 6-2 startup circuit v cc winding circuit and la tched shutdown release figure 11 shows the st artup circuit and v cc winding circuit. the current input from the ac line flows to the m-power2a through startup resistor r1 and charges electrolytic capacitor c2. the ic starts operating when this vo ltage reaches the on threshold voltage (v cc(on) ) and then power is supplied to the ic from the transformer's auxiliary winding. a low control ic current consumption has been achieved by converting the control ic to cmos. a current can be su pplied below v cc(on) to charge the electrolytic capacitor with an extremely small current consumption. we recommend setting the v cc winding voltage so that the v cc terminal voltage is between 19.0 and 20.0v at normal operation. (refer to the current diagra ms in the specifications for more details on current consumption.) figure 12 shows an example voltage waveform at the v cc terminal at startup. operation starts and the current consumption increases when v cc reaches v cc(on) . after operation starts the v cc terminal voltage begins to drop and continues to drop until power starts be ing supplied from the v cc windings. if v cc drops below v ccl(off) at this point, the uvlo will stop the co ntrol circuit and the star tup will fail, so startup resistor r1 and capacitor c2 must be set so that v cc does not drop below v ccl(off) . furthermore the resist ance of r2 in the v cc winding circuit (see figure 11) must be 2.2 or higher. so capacitor c2 holds no charge at startup the vw vo ltage (described below) will be difficult to generate a nd normal operation will be impossible (due to the arm short circuit protection). in addition make a poor coupling between the v cc winding and the secondary windings (s1 and s2) and a tight coupl ing between the v cc winding and the pr imary winding (p1). since the m-power2a ic is a cmos type connect a capacitor c3 with a capacitance of at least 0.1 f to the v cc terminal. a latched shutdown will be maintained as long as v cc is above v cc(la) . to maintain the latched shutdown select a startup resistor that will produc e a current higher than t he latch hold current (40 to 60 a) so that v cc will be above v cc(la) . refer to the v cc -i cc (latched shutdown ) diagram in the specifications for details . to release the latch v cc must be decreased below v cc(la) . v cc(on) v ccl(off) v cc time v cc winding voltage start of operation start up failure fig. 12 example waveform at vcc terminal at startup p3 8 10 vcc p gnd c1 c2 r1 r2 vw tr rectifier circuit or pfc c3 fig.11 startup and vcc winding circuit example
quality is our message mt5f18467 -20- 6-3 q2 gate pin: q2 drive circui t and q2 drive winding (p2 winding) ? q2 drive circuit figure 13 shows an example of q2 drive circuit. the following procedures show how to set the circuit constants for the circuit in figure 13. the resistances of r3 and r6 determine q2 turn-off speed. we recomme nd a resistance of r3 about 22 and that of r6 about 47 . these are the same value as the ic output stage resistance when q1 turns off. the resistances of r4 and r6 determine q2 turn-on speed. use the following two conditions. r4 must satisfy both conditions. condition 1: set r4 and r6 so that q2 turns on after q1 turns off and while current is still flowing through q2's body diode. condition 2: set r4 and r6 so that an arm short circuit does not oc cur at startup when q2 turns on. verify that the v cc winding's electrolytic capacitor (c2 in figure 11) is completely charged at startup. we recommend setting the r4 value between 150 and 470 . the r5 resistor is inserted so th at the q2 gate voltage will not rise at the dv/dt of q2's drain voltage rate. we recommend se tting the r5 value about 22k . figure 14 shows anothe r q2 drive circuit preventing a reverse voltage across the gate to source of q2 when the switch is off. this drive circuit is recommended when an input voltage (ed) range is wide. when the p2 volt age is negative the diode d12 is on and the transistor tr1 turns on. thus the q2 gate to source voltage is zero. we recommend r16 is 2.2 , r13 is 4.7k (1/2w), d13 is high speed switchi ng type which capacitance between terminals is less than 10pf and tr1 is a pnp transistor (v ce = -50v, i c = -0.5a, f t min=100mhz). q2 r3 c r p1 p2 t r 20 22 18 19 23 r4 r5 r6 zd1 zd2 d1 d2 d2 g2 d1 s2 d1 s2 fig. 13 q2 drive circuit tr1 c r p1 p2 t r 22 19 23 r14 r13 r16 d12 d11 d2 d2 d1 s2 d1 s2 q2 g2 18 20 fig. 14 q2 drive circuit
quality is our message mt5f18467 -21- ? q2 drive winding (p2 winding) set the p2 winding's maximum voltage (vp2(max)) below the q2 gate's absolute maximum rating (v gs ); we recommend setti ng vp2(max) between 80% and 90% of v gs . the p2 winding generates its maximum voltage when the dc bus voltage (c1 voltage) is at its maximum value (edc) and q1's on duty is small. when q1 is on a voltage close to ed is being applied to the main winding (p1 winding). use the following equation to calculate th e number of wind ing turns in the q2 drive winding. edc(max)/2 1 2 np np P vgs 0.8 0.9 < q2 gate's abso lute maximum rating (v gs ) edc(max) is the maximum valu e of the dc bus voltage. np1 is the number of winding turns in the main windin g (p1 winding). np2 is the number of winding turns in the q2 drive wind ing (p2 wi nding). select zener diodes zd1 and zd2, shown in figure 13, with the ze ner voltage that is below the q2 gate's absolute maximum rating a nd below vp 2(max). 6-4 vw pin figure 15 shows an example of vw terminal drive circuit. a comparator (vwcp) is connected internally to the vw terminal. vwcp compares the threshold value with the vw terminal voltage and turns q1 on or off (forced off). q1 on threshold: vwh is 1.56v (typical). q1 off threshold: vwl is 0.56v (typical). the power supply for vwcp is the v ref voltage so the absolute maximum rating of the vw terminal is minimum voltage of v ref voltage (4.75v). thus as shown in figure 15 insert a zener diode zd3 that break down voltage is less than 4.5v. to delay q1 turns on a capacitor c4 is added in this te rminal. we recommend c4 is 820pf. make the resistance of r7 as small as possible so that the vw terminal voltage exceeds vwh even when the v cc winding voltage is low. to force off q1 when the vw terminal voltage is less than vwl make the resistance of r8 as small as possible. we recommend setting r7 r8 r9 an d zd3 to the following values. r7: 10 k r8: 1k to 5.6 k r9: 100 k zd3: 3.9v these are recommended values. veri fy that there are no proble ms by testing the circuits. 8 15 c4 p gnd vw vwh vwl vw cp p3 d2 r7 tr zd3 r8 r9 s gnd fig. 15 vw terminal drive circuit
quality is our message mt5f18467 -22- 6-5 con pin connect capacitor c (con) between the con terminal and s gnd terminal to set the maximum q1 on width:t on . figure 16 shows the relationship between t on and c (con) .the t on setting is determined so that the power supp ly can supply the maximum required load using minimum dc bus capacitor voltage. it is possible to verify experimentally that the output voltage does not decrease under the conditions outlined above. the capacitance of c (con) must be above 1000pf. 6-6 vref pin the m-power2a ic is a cmos ic, so connect a ca pacitor c5 to vref terminal as shown in figure 17. we recommend a c5 capacitance above 1 f. 6-7 is pin is terminal is the over current detection terminal which is negative voltage to p gnd. connect s1 terminal and p gnd. insert the resistor rs between c1 minus terminal and p gnd terminal and low pass fi lter circuit composed of c6 and r10 as shown in figure 18. the resistance of rs is deter mined as following equation. in this equation vo c is the over current detection voltage vref 11 s gnd 7 c5 fig. 17 vref terminal is p gnd r10 c6 8 rs 12 s1 s1 5 4 id1 c1 iis fig. 18 is terminal c (con) -t on max 0 10 20 30 40 50 2000 3000 4000 5000 6000 7000 c (con) [pf] t on max[ s] fig. 16 relationship between t on and c (con) . 1 ) ( 10 id v i r rs oc is + =
quality is our message mt5f18467 -23- and iis is the current flow ing from is terminal to r10. iis is about 20ua. t he over current detection is negative voltage but voc is equal to pl us 0.168v when using the above equation. id1 is a current flowing through q1and id1 is decreased when input volt age is minimum. thus determine the resistance of rs when input voltage is minimum rated. the co rner frequency of the filter circuit composed of c6 and r10 is shown in the following equation. setting c6 and r10 is determined as fs should be between 100k hz and 1mhz. we recommend c6 is 1000 pf and r10 is 1k . 6-8 fb pin: feedback control figure 19 shows an example of the circuit in the vicinity of the fb terminal. the fb terminal is the input terminal for the feedback signal of the secondary's constant voltage control ci rcuit. to prevent improper operation due to no ise, insert a filt er composed of a capacitor c7 and resistor r11 as shown in figure 19. it is also needed to proper operation in a printed circuit board layout consider ation that current paths from pc1 to fb and s gn d terminals must be as near as possible and the pat hs must not be laid out under a transformer. fb pc1 13 s gnd 7 r11 c7 fig. 19 fb terminal 6 10 2 1 c r fs =
quality is our message mt5f18467 -24- warning 1. this data book contains the product specifications characterist ics data materials and structures as of january 2007. the contents are subject to change without notice due to changes in specifications or other reasons. when using a product li sted in this data bo ok be sure to obtain the latest specifications. 2. all applications described in this data book exemplify the us e of fuji's products for your reference only. no right or lice nse either express or implied un der any patent copyright trade secret or other intellectual property right owned by fuji electric co ., ltd. is (or shall be deemed) granted. fuji makes no represent ation or warranty whether expre ss or implied relating to the infringement or alleged infringemen t of other's intellectual proper ty rights, which may arise from the use of the applicat ions described herein. 3. although fuji electric contin ually strives to enhanc e product quality and reliability, a small percentage of semiconductor products may become faulty. when using fuji electric semiconductor products in your equipment you must ta ke adequate safety measures to prevent the equipment from causin g physical injury fire or other probl ems if any of the products become faulty. it is recommended to make your design fail-safe flame retardant and free of malfunction. 4. the products introduced in this data book are intended for use in the following electronic and electrical equipment requ iring normal reliability. computers, oa equipmen t, communications equipm ent (terminal devices) measurement equipment, machine tools, audio visual equipmen t, electrical home appliances personal equipment, indu strial robots and etc 5. if you need to use a product in this data book for equipment requiring higher reliability than normal such as for the equipment listed below it is imperative to contact fuji el ectric to obtain prior approval. when using these products for su ch equipment take adeq uate measures such as a backup system to prevent the equipment from malfunctioning even if a fuji's product incorporated in the equipment becomes faulty. transportation equipment (mounted on cars and ships), trunk commu nications equipment traffic-signal control equipment, gas leak age detectors with an auto-shut-off feature emergency equipment for respond ing to disasters and anti-burglar y devices, safety devices 6. do not use products in this data book for the equipment requiring strict reliability such as the following (with out exception). space equipment, aeronautic equi pment, atomic control equipment submarine repeater equi pment, medical equipment 7. copyright ? 2007 by fuji electric co., ltd. all rights reserved. no part of this data book may be reproduced in any form or by any means without the express wr itten permission of fuji electric.

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